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2009 Microchip Technology Inc.

DS39636D-page 133

PIC18F2X1X/4X1X

14.2

Capture Mode

In Capture mode, the CCPRxH:CCPRxL register pair

captures the 16-bit value of the TMR1 or TMR3

registers when an event occurs on the corresponding

CCPx pin. An event is defined as one of the following:

every falling edge

every rising edge

every 4th rising edge

every 16th rising edge

The event is selected by the mode select bits,

CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture

is made, the interrupt request flag bit, CCPxIF, is set; it

must be cleared in software. If another capture occurs

before the value in register CCPRx is read, the old

captured value is overwritten by the new captured value.

14.2.1

CCP PIN CONFIGURATION

In Capture mode, the appropriate CCPx pin should be

configured as an input by setting the corresponding

TRIS direction bit.

14.2.2

TIMER1/TIMER3 MODE SELECTION

The timers that are to be used with the capture feature

(Timer1 and/or Timer3) must be running in Timer mode or

Synchronized Counter mode. In Asynchronous Counter

mode, the capture operation will not work. The timer to be

used with each CCP module is selected in the T3CON

register (see Section 14.1.1 “CCP Modules and Timer

Resources”).

14.2.3

SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCPxIE interrupt enable bit clear to avoid false inter-

rupts. The interrupt flag bit, CCPxIF, should also be

cleared following any such change in operating mode.

14.2.4

CCP PRESCALER

There are four prescaler settings in Capture mode; they

are specified as part of the operating mode selected by

the mode select bits (CCPxM3:CCPxM0). Whenever

the CCP module is turned off or Capture mode is dis-

abled, the prescaler counter is cleared. This means

that any Reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared; therefore, the first capture may be from

a non-zero prescaler. Example 14-1 shows the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 14-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

(CCP2 SHOWN)

FIGURE 14-1:

CAPTURE MODE OPERATION BLOCK DIAGRAM

Note:

If RB3/CCP2 or RC1/CCP2 is configured

as an output, a write to the port can cause

a capture condition.

CLRF

CCP2CON

; Turn CCP module off

MOVLW NEW_CAPT_PS ; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF CCP2CON

; Load CCP2CON with

; this value

CCPR1H

CCPR1L

TMR1H

TMR1L

Set CCP1IF

TMR3

Enable

Q1:Q4

CCP1CON<3:0>

CCP1 pin

Prescaler

÷ 1, 4, 16

and

Edge Detect

TMR1

Enable

T3CCP2

CCPR2H

CCPR2L

TMR1H

TMR1L

Set CCP2IF

TMR3

Enable

CCP2CON<3:0>

CCP2 pin

Prescaler

÷ 1, 4, 16

TMR3H

TMR3L

TMR1

Enable

T3CCP2

T3CCP1

T3CCP2

T3CCP1

TMR3H

TMR3L

and

Edge Detect

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